1. Field of the Invention
The present invention relates to a phase-change memory device and a method of manufacturing a phase-change memory device.
2. Description of the Related Art
Phase-change memory devices employ in their memory cells a phase-change layer (a chalcogenide semiconductor thin film or the like) whose electrical resistance changes depending on its state. Chalcogenide semiconductors are amorphous semiconductors including chalcogen elements.
FIG. 1 of the accompanying drawings shows a portion of the periodic table which is illustrative of chalcogen elements. As shown in FIG. 1, chalcogen elements include S (Sulfur), Se (Selenium), and Te (Tellurium) in group 6 in the periodic table. Chalcogenide semiconductors are used in generally two fields, optical disks and electric memories. Chalcogenide semiconductors used in the field of electric memories include GeSbTe (hereinafter referred to as “GST”) which is a compound of Ge (Germanium), Te (Tellurium), and Sb (Antimony), AsSbTe, SeSbTe, etc.
FIGS. 2A and 2B of the accompanying drawings are diagrams illustrative of the principles of a phase-change memory.
As shown in FIG. 2A, a chalcogenide semiconductor can take two stable states, i.e., amorphous state 10 and crystalline state 30. For switching from amorphous state 10 to crystalline state 30, the chalcogenide semiconductor needs to be supplied with heat in excess of energy barrier 20.
As shown in FIG. 2B, the amorphous state exhibits a higher electrical resistance corresponding to a digital value “1” and the crystalline state exhibits a lower electrical resistance corresponding to a digital value “0”. This allows the chalcogenide semiconductor to store digital information. The amount of current flowing through the chalcogenide semiconductor or a voltage drop across the chalcogenide semiconductor is detected to determine whether the information stored in the chalcogenide semiconductor is “1” or “0”.
Heat supplied to cause a phase change in the chalcogenide semiconductor is Joule heat. Specifically, pulses having different peak values and different pulse durations are applied to the chalcogenide semiconductor to generate Joule heat in the vicinity of contact surfaces of the electrodes and the chalcogenide semiconductor, and the Joule heat causes a phase change.
Specifically, after the chalcogenide semiconductor is supplied with heat at a temperature near its melting point, when the chalcogenide semiconductor is quickly cooled, it switches into the amorphous state. After the chalcogenide semiconductor is supplied with heat at a crystallizing temperature lower than the melting point for a long period of time, when the chalcogenide semiconductor is cooled, it switches into the crystalline state. For example, after the GST is supplied with heat at a temperature near the melting point (about 610° C.) for a short period of time (1 through 10 ns), when the GST is quickly cooled for about 1 ns, it switches into the amorphous state. After the GST is supplied with heat at a crystallizing temperature (about 450° C.) for a long period of time (30 through 50 ns), when the GST is cooled, it switches into the crystalline state.
As shown in FIG. 2B, switching from the amorphous state into the crystalline state is referred to as “setting” (crystallizing process), and a pulse applied to set the chalcogenide semiconductor is referred to as a “setting pulse”. It is assumed that the minimum temperature (crystallizing temperature) required to crystallize the chalcogenide semiconductor is represented by Tc, and the minimum time (crystallizing time) required to crystallize the chalcogenide semiconductor is represented by tr. Conversely, switching from the crystalline state into the amorphous state is referred to as “resetting” (amorphizing process), and a pulse applied to reset the chalcogenide semiconductor is referred to as a “resetting pulse”. Heat applied to the chalcogenide semiconductor for resetting the chalcogenide semiconductor is heat at a temperature near the melting point Tm. After the chalcogenide semiconductor is melted, it is rapidly quenched.
FIGS. 3A through 3D of the accompanying drawings are diagrams illustrating a basic structure of a phase-change memory device and the manner in which the phase-change memory device is set and reset.
As shown in FIG. 3A, the phase-change memory device is of a basic structure having chalcogenide semiconductor layer (phase-change layer) 46 sandwiched between upper and lower electrodes 48, 42. Lower electrode 42 is mounted on substrate 40 and isolated from upper electrode 48 by electric insulating film 44. Upper electrode 48 is connected to terminal P to which a setting pulse will be applied. Lower electrode 42 is connected to ground (reference electrode).
As shown in FIG. 3B, the phase-change memory device shown in FIG. 3A is equivalent to resistor R1. The resistance of resistor R1 varies depending on whether chalcogenide semiconductor layer 46 is in the amorphous state or the crystalline state. Setting pulse S1, i.e., a pulse having a peak value in excess of threshold value Vth, resetting pulse S2, i.e., a pulse having a peak value greater than setting pulse S1 and a shorter pulse duration than setting pulse S1, and reading pulse S3, i.e., a pulse having a peak value smaller than threshold value Vth and a longer pulse duration than setting pulse S1, are selectively applied to terminal P. Threshold value Vth represents a lower-limit voltage at which Joule heat required for crystallization can be generated.
FIG. 3C shows the relationship between setting pulse S1 and a temperature rise caused by the Joule heat that is generated when setting pulse S1 is applied to terminal P. In FIG. 3C, the upper curve represents the waveform of the voltage of setting pulse S1, and the lower curve 51 represents the manner in which the temperature increases due to the Joule heat.
The voltage value of setting pulse S1 is in excess of threshold value Vth, and the pulse duration of setting pulse S1 is represented by tcry. Pulse duration tcry is equal to or longer than crystallizing time tr, i.e., the minimum time required to crystallize the chalcogenide semiconductor. The temperature rise due to the Joule heat is considerably lower than melting point Tm and higher than minimum temperature Tc required for crystallization (crystallizing temperature).
Similarly, FIG. 3D shows the relationship between resetting pulse S2 and a temperature rise caused by the Joule heat that is generated when resetting pulse S2 is applied to terminal P. In FIG. 3D, the upper curve represents the waveform of the voltage of resetting pulse S2, and the lower curve 53 represents the manner in which the temperature increases due to the Joule heat.
As shown in FIG. 3D, resetting pulse S2 has a peak value much higher than threshold value Vth and a sufficiently small pulse duration. The temperature rise due to the Joule heat is in excess of melting point Tm of the chalcogenide semiconductor. The temperature falls from the peak value to crystallizing temperature Tc within sufficiently short time Tamo. Therefore, after the chalcogenide semiconductor is melted, it is quenched so that it returns to the amorphous state.
The phase-change memory device shown in FIGS. 3A through 3B has a circuit arrangement for supplying setting pulse S1 and resetting pulse S2 from terminal P. However, the phase-change memory device may have a circuit arrangement as shown in FIG. 4 of the accompanying drawings.
FIG. 4 is a circuit diagram of a circuit arrangement of the phase-change memory device.
In FIG. 4, resistor R1 is equivalent to the phase-change memory device and has an end connected to terminal P connected to power supply potential VDD. Resistor R1 has the other end connected to size-adjusted MOS transistors M1, M2, M3 having respective gates connected to setting pulse terminal P1, resetting pulse terminal P2, and reading pulse terminal P3, respectively.
Setting, resetting, and reading pulse signals are selectively applied to setting pulse terminal P1, resetting pulse terminal P2, and reading pulse terminal P3, respectively, to select which one of MOS transistors M1, M2, M3 is to be turned on, and to control the turn-on time of a selected one of MOS transistors M1, M2, M3. In this manner, the phase-change memory device operates in the setting, resetting, and reading modes.
FIG. 5 of the accompanying drawings is a circuit diagram showing the manner in which a phase-change memory device (phase-change memory IC) operates in a reading mode. Those parts shown in FIG. 5 which are identical to those shown in FIGS. 3A through 3D and 4 are denoted by identical reference characters.
In FIG. 5, a word line is represented by W, a ground line by G, a bit line (a pulse input line connected to terminal P for inputting setting pulse S1, resetting pulse S2, and reading pulse S3) by B, and a resistor equivalent to the phase-change memory device (comprising chalcogenide semiconductor layer 60) which serves as a memory cell by R1.
An NMOS transistor (switching device) for selecting a memory cell is represented by M4, a current-to-voltage converting resistor by R2, a sense amplifier by A1, a reference voltage source for sense amplifier A1 by 62, a current flowing through the memory cell in the reading mode by I1, and an output voltage of sense amplifier A1 (sensing output) by Vout.
In the setting mode (also in the resetting mode and the reading mode), word line W is activated to turn on NMOS transistor M4. Thereafter, one of pulses S1, S2, S3 is supplied from terminal P. In the reading mode, reading pulse S3 is supplied from terminal P.
The resistance of resistor R1 varies and hence the amount of current I1 flowing therethrough varies depending on whether chalcogenide semiconductor layer 60 of the memory cell is in the amorphous state or the crystalline state. By converting the amount of current I1 into a voltage and reading the voltage, it is possible to determine whether information stored in the memory cell is “1” or “0”.
FIG. 6 of the accompanying drawings is a fragmentary cross-sectional view showing specific structural details of a memory cell provided by a phase-change memory device (phase-change memory IC).
In FIG. 6, p-type semiconductor substrate 70 has n-type source layer 71 and n-type drain layer 72 disposed therein, and gate electrode 74 connected to word line W is disposed on gate insulating film 73 that is disposed on p-type semiconductor substrate 70.
Interlayer insulating films 75, 79 are disposed on gate insulating film 73. An electrode connected to n-type source layer 71 comprises contact plug 76 extending through interlayer insulating film 75 and gate insulating film 73 and electrode 78 connected to contact plug 76 and comprising a first conductive layer disposed in interlayer insulating film 79. The electrode is connected to ground line G.
Contact plug 77 made of tungsten (W), for example, extends through interlayer insulating film 75 and is connected to n-type drain layer 72. Contact plug 80 serving as a heater electrode extends through interlayer insulating film 79 and is connected to contact plug 77.
Phase-change layer 82 comprising a chalcogenide semiconductor is disposed on interlayer insulating film 79 with adhering layer 81 in the form of a thin metal film being interposed therebetween. Adhering layer 81 is interposed to hold phase-change layer 82 and interlayer insulating film 79 closely together because phase-change layer 82 and interlayer insulating film 79 will not adhere closely to each other.
Upper electrode 83 comprising a second conductive layer is disposed on phase-change layer 82 and extends over its upper surface. Interlayer insulating film 84 is disposed on upper electrode 83. Contact plug 85 connected to upper electrode 83 extends through interlayer insulating film 84. Electrode 86 comprising a third conductive layer is disposed on interlayer insulating film 84 and connected to contact plug 85. Electrode 86 serves as pulse supply terminal P. Contact plug 85 and electrode 86 jointly make up a contact electrode.
Phase-change layer 82 includes a region surrounded by thick dotted line X, where a phase change occurs. Electrode 80 made of titanium nitride (TiN) is embedded in interlayer insulating film 79. Electrode 80 constricts a current flowing through phase-change layer 82 to increase the current density for efficiently generating Joule heat in phase-change region X. Therefore, electrode 80 is called a heater electrode (heating electrode), and will hereinafter referred to as heater electrode 80.
The current density of the current flowing through phase-change layer 82 increases and the generated Joule heat increases as the area of contact between heater electrode 80 and phase-change layer 82 decreases. Consequently, the area of contact between heater electrode 80 and phase-change layer 82 is set to a sufficiently small area, e.g., an area determined by photolithographically designed minimum dimensions.
A phase-change memory device with the phase-change layer sandwiched between the upper and lower electrodes is disclosed in Japanese laid-open patent publication No. 2003-332529, for example. The publication also discloses that the lower electrode (heater electrode) has a pointed end to minimize the area of contact between the electrode and the phase-change layer in order to prevent the thermal efficiency from being lowered in the phase-change process of the phase-change memory device.
The inventor of the present invention has studied the phase-change memory device shown in FIG. 6 and found that it suffers various disadvantages as described below.
The phase-change memory device shown in FIG. 6 has a heat radiation route for transmitting heat generated in phase-change region X of phase-change layer 82 downwardly through heater electrode 80 to contact plug 77 and for radiating the heat from contact plug 77. The heat radiation route necessarily occurs because of the structure of the phase-change memory device.
It should be noted that contact plug 77 and heater electrode 80 are made of different materials, and the heat radiation capability of contact plug 77 is high due to the different materials.
Specifically, contact plug 77 is made of a material of low resistance, e.g., tungsten, for the purpose of reducing the electrical resistance of contact plug 77, and heater electrode 80 is made of a material of high resistance, e.g., titanium nitride, for the purpose of efficiently generating Joule heat. Since a metal material having a higher electrical conductivity (the reciprocal of electrical resistivity) has a higher thermal conductivity, contact plug 77 having a lower resistance, i.e., a higher electrical conductivity, has a higher thermal conductivity than heater electrode 80 having a higher resistance, i.e., a lower electrical conductivity. Therefore, contact plug 77 functions as a heat sink (heat radiating fin) having good heat radiating capability.
Inasmuch as a phase change of the chalcogenide semiconductor is caused by Joule heat generated when a current flows therethrough, it is not preferable for Joule heat to be radiated through the heater electrode and the contact plug and interconnections positioned beneath the heater electrode because the heat radiation would lead to a reduction in thermal efficiency.
Such a reduction in thermal efficiency does not pose a significant problem when a single phase-change memory device or a phase-change memory IC of low integration degree is made as a prototype. However, it could be a large problem when highly integrated phase-change memory ICs are actually mass-produced according to a microfabrication process.
Specifically, for manufacturing a phase-change memory device having high storage capacity, it is necessary to reduce the size of a memory cell, and it is important to reduce the resetting current, i.e., a current required to shift the phase-change layer from the crystalline state to the amorphous state. The structure wherein the contact electrode layer held in contact with the bottom surface of the phase-change layer functions as a heat sink (heat radiating fin) having good heat radiating capability is responsible for reducing the thermal efficiency and for preventing the amount of resetting current from being reduced.
If, on the other hand, the contact plug is made of a material of high resistance to reduce heat radiation from the contact plug, i.e., to increase the thermal efficiency, then the contact resistance between the contact plug and the semiconductor substrate increases, and the current flowing therethrough decreases. In this case, the size (width/length) of the transistor for selecting the memory cell needs to be increased, posing an obstacle to efforts to reduce an element size, i.e., to increase the storage capacity of the phase-change memory device.
It is thus difficult to design a phase-change memory device having suppressed heat radiation immediately below the heater electrode and reduced contact resistance between the heater electrode and the semiconductor substrate.
One solution is to bring contact plug 77 of tungsten, which is held in contact with the drain layer of an NMOS transistor, into contact with heater electrode 80 through a new contact plug made of the same material (TiN) as heater electrode 80, rather than into direct contact with heater electrode 80.
Specifically, for electrically connecting the semiconductor substrate and the heater electrode to each other, a contact plug of low resistance, made of tungsten, for example, having reduced contact resistance between itself and the semiconductor substrate is provided, and another contact plug made of the same material, e.g., titanium nitride, as the heater electrode is disposed on the contact plug having low resistance. The heater electrode made of titanium nitride, for example, is disposed on the contact plug having high resistance.
However, since the two contact plugs disposed in respective different layers are present between the semiconductor substrate and the heater electrode, the number of layers of the phase-change memory device increases, and the number of man-hours required to manufacture the phase-change memory device also increases. Furthermore, the two contact plugs may possibly be shifted in position with respect to each other. Accordingly, difficulty arises in mass-producing large-scale phase-change memory devices of this design.
The invention disclosed in Japanese laid-open patent publication No. 2003-332529 addresses heat radiation in the contact interface between the phase-change layer and the heater electrode, and does not refer to or suggest radiation of heat transmitted through the heater electrode from the lower electrode, as addressed by the present invention. The disclosure of the above publication does not present any solution to the radiation of heat referred to above. According to the disclosure of the above publication, the end of the heater electrode needs to be pointed at a sharp angle. The need to produce a heater electrode having a pointed end, however, tends to make a method of manufacturing a phase-change memory device complex.